Field of the Invention
The present invention relates to a display apparatus, and more particularly, to a source driver for a display apparatus, which stably performs a function of processing display data at a high speed and achieving a large screen and is insensitive to power noise.
Description of the Related Art
As a display apparatus for displaying an image, a liquid crystal display apparatus has been extensively used.
A conventional liquid crystal display apparatus includes a timing controller that processes a data signal and generates a timing control signal, and a panel driving unit that drives a display panel by using the data signal and the timing control signal transmitted from the timing controller.
The panel driving unit includes a source driver that processes the data signal and a gate driver that controls a source driving signal to be driven to the display panel. Each of the timing controller, the source driver, and the gate driver may be prepared in the form of an integrated circuit.
The source driver concentrically outputs a voltage for displaying an image to the display panel at a specific time in terms of operation characteristics thereof. The source driver has a large number of output ports for driving data lines of the display panel. That is, the source driver concentrically outputs the voltage for displaying an image from the large number of output ports at the specific time. Therefore, when the display panel is driven, power noise occurs in the source driver. The power noise occurring in an interior as described above or power noise introduced from an exterior may have an influence on the operation of the source driver.
In the conventional liquid crystal display apparatus, the transmission speed of the data signal from the source driver is not fast, and the size of the display pane is small. Therefore, the source driver has no difficulty of detecting the data signal regardless of the aforementioned power noise, and it is not probable that an abnormal operation is performed.
Furthermore, in the conventional liquid crystal display apparatus, a clock signal necessary for detecting the data signal is also transmitted to the source driver from the timing controller through an independent signal line. In this regard, the source driver has a characteristic tolerant to the power noise.
A large liquid crystal display apparatus having a high refresh rate needs to perform transmission/reception of a data signal between the timing controller and the source driver at a high speed. To this end, the liquid crystal display apparatus may use various interfaces, and for example, may use a clock embedded data signaling (CEDS) interface in which the clock signal has been embedded in the data signal. That is, the timing controller transmits a clock embedded data signal (hereinafter, referred to as a ‘CED signal’), in which the clock signal has been embedded in the data signal, to the source driver.
In an interface environment employing the aforementioned CEDS scheme, the source driver receives the CED signal, recovers the clock signal and the data signal from the CED signal, processes the data signal by using the recovered clock signal, and outputs a source driving signal. However, in the aforementioned interface environment employing the CEDS scheme, the source driver has a problem that it is not tolerant to power noise.
When large power noise occurs in or is introduced to the source driver, it is probable that the source driver instantaneously performs an abnormal operation by the power noise in the process of recovering the clock signal from the CED signal and detecting the data signal.
The abnormal operation of the source driver by the power noise will be described in more detail below.
The liquid crystal display apparatus has several power sources, and particularly, has high voltage sources for driving the display panel.
These high voltage sources may be used for parts mounted on the same printed circuit board for different purposes, and power noise may occur when switching is performed in the parts by the high voltage sources.
For example, the liquid crystal display apparatus may have high voltage sources of 9 V, 4.5 V, 24 V and the like. The source driver has a clock-data recovery circuit therein for the CEDS interface. The clock-data recovery circuit recovers the clock signal and the data signal from the CED signal, and uses a relatively low voltage of 1.8 V at this time.
Even when power noise of about 10% of the high voltage source occurs, power noise of 0.9 V, 0.45 V, 2.4 V and the like may occur. When such power noise has an influence on the clock-data recovery circuit in the source driver, the clock-data recovery circuit may perform an abnormal operation such as abnormal detection of the data signal.
Particularly, the power noise may occur when the source driver concentrically outputs the source driving signal at a specific time in order to drive the display panel.
For example, when the output of an amplifier of the source driver using the high voltage source in order to output the source driving signal is transitioned from Low to High (for example, 9 V), power noise may occur in a ground voltage GND. When such power noise is introduced to the clock-data recovery circuit of the source driver, lock fail may occur in the clock-data recovery circuit.
A lock state indicates a state in which, when the clock signal recovered from the CED signal maintains a stable state, the clock signal in the recovered state is set to be continuously outputted. The lock fail indicates that the lock state is released by the influence of power noise even though the clock signal maintains a stable state.
In the case in which the aforementioned power noise is introduced, since the lock state is released by the lock fail even though the clock signal is stable, the source driver may perform an abnormal operation such as clock training for stabilizing of the clock signal.
For example, in the case in which the output voltage of the amplifier of the source driver is 9 V, even when power noise of 0.451 V, which corresponds to about 5% of the output voltage of the amplifier of the source driver, occurs, the aforementioned lock fail may occur in the clock-data recovery circuit of the source driver at a corresponding time point.
In this regard, the source driver needs to be designed to be insensitive to power noise in order to achieve a high speed operation and a large screen.